The present invention relates generally to lock detectors for phase lock loops and, more particularly, to a lock detector which establishes upper and lower bounds to a lock range in order to ensure that phase error is substantially confined within the range before acquisition of lock is declared.
Phase lock loops (PLLs) and clock recovery circuits (CRCs) have found wide application in such diverse areas as digital communication systems, wireless systems, digital circuits and data recovery systems for use in connection with mass storage media such as hard disk, tape and optical drives. In the field of digital communication systems, phase lock loops are typically used in modern digital communications receivers to recover useful data from a transmission signal stream by providing data recovery circuitry with a timing reference having the appropriate frequency and phase characteristics so as to match timing characteristics of the transmitted signal and thus, ensure proper data recovery.
In modern HDTV signal transmissions, a receiver must be capable of locking onto a transmitter""s pilot carrier phase as well as the transmitter""s timing phase. Locking the receiver to the transmitter""s carrier phase is commonly referred to as carrier phase recovery, whereas locking onto the timing phase of the transmitter is referred to as timing phase recovery. Both of these functions are critical to a modern day communications system since the receiver must be synchronized to the transmitter in order that transmitted data may be correctly demodulated, and equalized.
Applications of phase lock loops (or more correctly frequency-phase locked loops, FPLLs) in a modern high-speed communications system would include their use as frequency acquisition tools in a receiver""s channel tuner and as an automatic gain control (AGC) loop, disposed within a channel tuner, which ensures that the power level of a received signal is suitably limited to a particular desired level. Thus, it can be seen that PLLs and FPLLs play a significant role in the effective operation of various portions of a modern digital communication system. Indeed, it is difficult to conceive of a modern high-speed digital communications system that does not make extensive use of precision PLLs.
Notwithstanding the necessity of their use in modern communication systems, conventional PLLs suffer from a particular disadvantage that makes their use in modern, high-speed communication systems problematic. This disadvantage relates most particularly to the time characteristics of the phase error response of a first order or second order PLL in response to a prompt change in the phase of an input signal. Given the extremely precise phase and timing alignments required in modern high-speed communication systems, and their correspondingly small phase error margins, a false designation of phase lock during a phase acquisition procedure can very easily result in the loss of system timing and a consequent disruption of, for example, carrier recovery operations and thus, a loss of signal.
The present invention is directed to a system and method for evaluating phase detector output so as to optimally determine when phase lock has been achieved. The novel lock detection system is suitable for incorporation in a phase locked loop of the type including a phase detector configured to develop phase error signals for use by, for example, a loop filter in deriving control signals for an oscillator circuit. A lock detector circuit evaluates phase error signals in order to determine whether a locked condition has been achieved on the basis of the output signal train of phase detector""s passing evaluation against a magnitude metric and a timing metric.
In one aspect of the invention, the lock detector circuit includes a summing circuit having at least one input for receiving phase error signals developed by the phase detector. The summing circuit combines the absolute value of an input phase error signal with a negative valued first limit signal which corresponds to the maximum allowable phase error during lock. Summation of the two signals gives rise to a negative-valued signal when the phase error signal is below the first limit and a positive-valued signal when the absolute magnitude of the input phase error signal is above the first limit.
The output of the summing circuit is compared to a zero reference signal and outputs in a first state when the summation result is less than zero and outputs a signal in a second state when the summation result is greater than zero. A summation result less than zero indicates that the absolute magnitude of an input phase error signal is less than the first limit signal and therefore converging toward zero.
In a further aspect of the invention, the comparison circuit signal in a first state initiates a time interval counter. The time interval counter is reset at any time the absolute magnitude of any phase error signal exceeds the first limit signal, i.e., at any time the summation result is greater than or equal to zero. Lock is declared after the time interval counter counts to the end of a specified time interval. Thus, phase error signals must not only converge to a value less than the first limit signal but also remain at a value below the first limit signal for a period of time equal to the time interval counter""s specified time interval.
In an additional aspect of the invention, a low pass filter is coupled between the lock detector and the phase detector circuit. The low pass filter averages phase error component values to remove extraneous high frequency noise and improve system performance. The output of the low pass filter is coupled to a conditioning circuit, such as a rectification circuit, which receives input phase error signals corresponding to both positive and negative phase relationships and conditions the phase error signal such that the output of the conditioning circuit represents their absolute magnitude.